1. Field of the Invention
The invention relates to a display technique. More particularly, the invention relates to a display, a pixel circuitry and an operating method of the pixel circuitry.
2. Description of Related Art
A flat panel display such as a liquid crystal display (LCD), a liquid crystal on silicon (LCOS) display, etc. has advantages of high image quality, small size, light weight, low driving voltage, and low power consumptions, etc., so that it is widely used in consumable communication or electronic products such as video cameras, personal digital assistants (PDAs), mobile phones, notebooks, display screens of desk-top computers and thin digital televisions, etc., and gradually replaces a cathode ray tube (CRT) technique to become a main stream in the display market.
Generally, when the LCOS display displays a frame by using a display frequency of 60 Hz, the frame may have a flicking phenomenon. To reduce the flicking phenomenon of the frame, the display frequency of the frame is increased to 120 Hz, so as to suppress the flicking phenomenon of the frame through a relatively high display frequency. Wherein, according to a method of increasing the display frequency, the same frame data is repeatedly transmitted to a source driver during two frame periods, and the source driver transmits the same frame data of different polarities to a display panel during the two frame periods respectively.
FIG. 1A is a system block diagram illustrating a conventional display. Referring to FIG. 1, a display device 100 includes a timing controller (T-con) 110, a source driver 120, a gate driver 130 and a display panel 140. The T-con 110 outputs a data signal DD to the source driver 120, and the source driver 120 correspondingly outputs a data voltage to the display panel 140, wherein the data voltage may have a positive polarity or a negative polarity. Now, the gate driver 130 is controlled by the T-con 110 to activate a pixel circuitry PX of the display panel 140 to receive the data voltage, and then drives the pixel circuitry PX of the display panel 140 to display according to the stored data voltage.
FIG. 1B is a driving timing diagram of the data signal DD and the pixel circuitry PX of FIG. 1A. During a data writing period dw1 of a frame period fp1, the data signal DD delivers a frame data F1, wherein the frame data F1 contains a first pixel data D1. Now, the source driver 120 outputs a positive polarity data voltage D1+ to the pixel circuitry PX of the display panel 140 according to the first pixel data D1. During a vertical blanking period vb1 of the frame period fp1 and a data writing period dw2 of a frame period fp2, the pixel circuitry PX is controlled by the gate driver 130 to display according to the positive polarity data voltage D1+.
During the data writing period dw2 of the frame period fp2, the data signal DD also delivers the frame data F1, and now the source driver 120 outputs a negative polarity data voltage D1− to the pixel circuitry PX of the display panel 140 according to the first pixel data D1. During a vertical blanking period vb2 of the frame period fp2 and a data writing period dw3 of a frame period fp3, the pixel circuitry PX is controlled by the gate driver 130 to display according to the negative polarity data voltage D1−.
According to the above descriptions, the source driver 120 receives the frame data F1 twice, so as to respectively output the positive polarity data voltage (for example, D1+) and the negative polarity data voltage (for example, D1−) during different frame periods (for example, the frame periods fp1 and fp2). Similarly, if the display device 100 is about to display a frame data F2 containing a second pixel data D2, the data signal DD delivers the frame data F2 twice to the source driver 120, so as to respectively generate a positive polarity data voltage (for example, D2+) and a negative polarity data voltage (for example, D2−). Moreover, the pixel circuitry PX is also controlled by the gate driver 130 to display according to the positive polarity data voltage (for example, D2+) and the negative polarity data voltage (for example, D2−) during different periods.
Since the pixel circuitry PX of the display device 100 can only store one data voltage during one frame period, the positive polarity data voltage and the negative polarity data voltage corresponding to the same pixel data are respectively transmitted to the pixel circuitry PX during two neighbouring frame periods. Therefore, while the display device 100 increases the display frequency of the frame, a data transmission rate of the source driver 120 is accordingly increased, so that a power consumption of the source driver 120 is correspondingly increased. Moreover, if the data transmission rate is excessively high, the data signal DD received by the source driver 120 can be distorted. Now, pins of the source driver 120 used for receiving the data signal DD can be increased to reduce the data transmission rate. However, increasing of the pins of the source driver 120 used for receiving the data signal DD not only increases a hardware cost of the display device 100, a circuit structure of the source driver 120 is also required to be correspondingly modified, so that a cost for circuit design is increased.